The present invention relates to a semiconductor integrated circuit device including an electrostatic discharge (ESD) protection circuit, and more particularly relates to a semiconductor integrated circuit device including an ESD protection circuit having an improved capability for protecting an input circuit, an output circuit, an input/output circuit and an internal circuit from ESD.
In recent years, in the processing of semiconductor integrated circuit devices, the level of integration has been increased in accordance with technical advances in miniaturization and achievement of higher density. Accordingly, semiconductor integrated circuit devices are vulnerable to damage caused by electrostatic discharge (hereinafter, called “surge”). For example, a surge penetrated from an external connection terminal might destroy an element such as an input circuit, an output circuit, an input/output circuit or an internal circuit, thus increasing the possibility of reduction in performance of the element. Therefore, if a semiconductor integrated circuit device is provided with an external connection terminal, the device often includes a protection circuit for protecting an input circuit, an output circuit, an input/output circuit or an internal circuit from a surge. Such a protection circuit is herein called an “electrostatic discharge protection circuit”.
FIG. 13 is an electric circuit diagram illustrating the configuration of an output circuit of a known semiconductor integrated circuit device including an electrostatic discharge protection circuit, and the periphery of the output circuit. As shown in FIG. 13, the known semiconductor integrated circuit device includes: an external connection terminal 101; an electrostatic discharge protection circuit 102; an output circuit 103; an output prebuffer circuit 104; an internal circuit 121; and an inter-power supply electrostatic discharge protection circuit 122. Herein, the “inter-power supply electrostatic discharge protection circuit” refers to the electrostatic discharge protection circuit located between a line through which a power supply voltage VDD is supplied and another line through a ground voltage VSS is supplied. The electrostatic discharge protection circuit 102 and the inter-power supply electrostatic discharge protection circuit 122 are provided so as to protect the output circuit 103 from a surge penetrated from the external connection terminal 101.
The electrostatic discharge protection circuit 102 is provided between the external connection terminal 101 and the output circuit 103, and includes a PMIS transistor 105, an NMIS transistor 106, a resistor 107 and a resistor 108. As used herein, “PMIS transistor” refers to a p-channel MIS transistor, and “NMIS transistor” refers to an n-channel MIS transistor. The PMIS transistor 105 includes: a source connected to a power supply line 119 through which the power supply voltage VDD is supplied; a gate connected to the power supply line 119 with the resistor 107 interposed therebetween; a drain connected to the external connection terminal 101; and a substrate region (n-well) connected to the power supply line 119. On the other hand, the NMIS transistor 106 includes: a source connected to a ground line 120; a gate connected to the ground line 120 with the resistor 108 interposed therebetween; a drain connected to the external connection terminal 101; and a substrate region (p-well) connected to the ground line 120.
The output circuit 103 is provided between the electrostatic discharge protection circuit 102 and the output prebuffer circuit 104, and includes a PMIS transistor 111 and an NMIS transistor 112. The PMIS transistor 111 includes: a source connected to the power supply line 119; a gate connected to an output terminal of a first prebuffer 115 of the output prebuffer circuit 104; a drain connected to the external connection terminal 101; and a substrate region (n-well) connected to the power supply line 119. On the other hand, the NMIS transistor 112 includes: a source connected to the ground line 120; a gate connected to an output terminal of a second prebuffer 117 of the output prebuffer circuit 104; a drain connected to the external connection terminal 101; and a substrate region (p-well) connected to the ground line 120.
The output prebuffer circuit 104 amplifies an output signal from the internal circuit 121, and is provided between the internal circuit 121 and the output circuit 103. The output prebuffer circuit 104 includes: a first prebuffer circuit 116 provided at its last stage with the first prebuffer 115; and a second prebuffer circuit 118 provided at its last stage with a second prebuffer 117. The first prebuffer 115 is provided with: a terminal which is connected to the power supply line 119 and through which a power supply voltage is supplied; a ground terminal connected to the ground line 120; an output terminal connected to the gate of the PMIS transistor 111 of the output circuit 103; and an input terminal connected to the internal circuit 121. On the other hand, the second prebuffer 117 is provided with: a terminal which is connected to the power supply line 119 and through which a power supply voltage is supplied; a ground terminal connected to the ground line 120; an output terminal connected to the gate of the NMIS transistor 112 of the output circuit 103; and an input terminal connected to the internal circuit 121. It should be noted that the first and second prebuffer circuits 116 and 118 are each provided with prebuffers whose number is determined in accordance with the degree of amplification of an output signal from the internal circuit 121. Output signals whose levels are the same or opposite to each other are sent from the output terminal of the first prebuffer 115 at the last stage of the first prebuffer circuit 116 and that of the second prebuffer 117 at the last stage of the second prebuffer circuit 118.
The inter-power supply electrostatic discharge protection circuit 122 is provided between the power supply line 119 and the ground line 120, and includes an NMIS transistor 123. The NMIS transistor 123 includes: a source connected to the ground line 120 for grounding; a gate connected to the ground line 120 with a resistor 124 interposed therebetween; a drain connected to the power supply line 119; and a substrate region (p-well) connected to the ground line 120.
In the known semiconductor integrated circuit device implemented as described above, a surge applied between the power supply line 119 and the external connection terminal 101 is absorbed due to the breakdown of the PMIS transistor 105, while a surge applied between the ground line 120 and the external connection terminal 101 is absorbed due to the breakdown of the NMIS transistor 106. Thus, the output circuit 103 is protected from a surge penetrated from outside through the external connection terminal 101.
Semiconductor integrated circuit devices must ensure, for users, resistance to destruction caused by surge, and thus need to meet ESD test standards. Recently, as the ESD test standards, human body model (HBM) test standards, typified by MIL standards, have been used as global standards, and therefore, semiconductor integrated circuit devices are required to meet such standards.
FIGS. 14A and 14B are a circuit diagram illustrating an evaluation circuit for carrying out an ESD test according to HBM test standards, and a graph showing an HBM discharge waveform obtained in carrying out the test according to the MIL test standards, respectively.
As shown in FIG. 14A, the evaluation circuit includes two sub-circuits provided in parallel with respect to a charge and discharge capacitor 151 having a capacitance C of 100 pF (one of the two sub-circuits is shown in the left hand part of FIG. 14A, while the other sub-circuit is shown in the right-hand part of FIG. 14A). The sub-circuit shown in the left-hand part of FIG. 14A is provided with a voltage-variable charge power supply 150, while the sub-circuit shown in the right-hand part of FIG. 14A is provided with a discharge resistor 153 having a resistance R of 1.5 kΩ. The evaluation circuit further includes a selector switch 152 connected to one electrode of the charge and discharge capacitor 151. Via the selector switch 152, a high-voltage section of the charge power supply 150 and the discharge resistor 153 are alternately connected to said one electrode of the charge and discharge capacitor 151. The other electrode of the charge and discharge capacitor 151 is connected to a low-voltage section of the charge power supply 150 in the sub-circuit shown in the left-hand part of FIG. 14A, and is connected to the discharge resistor 153 in the sub-circuit shown in the right-hand part of FIG. 14A. In the sub-circuit shown in the right-hand part of FIG. 14A, a device to be tested 154 is interposed between the other electrode of the charge and discharge capacitor 151 and the discharge resistor 153 and an ESD test is carried out on the device to be tested 154.
In carrying out an ESD test using this evaluation circuit, first, said one electrode of the charge and discharge capacitor 151 is connected to the charge power supply 150 via the selector switch 152. Thus, the sub-circuit shown in the left-hand part of FIG. 14A becomes a closed circuit, and the charge power supply 150 allows electrical charges to be accumulated in the charge and discharge capacitor 151. The charging voltage at this time is 4000 V, for example. Thereafter, said one electrode of the charge and discharge capacitor 151 is connected to the discharge resistor 153 via the selector switch 152. Thus, the sub-circuit shown in the right-hand part of FIG. 14A becomes a closed circuit, and the electrical charges accumulated in the charge and discharge capacitor 151 are applied to the semiconductor integrated circuit device, i.e., the device to be tested 154, through the discharge resistor 153.
In this case, the test is carried out in accordance with the waveform as shown in FIG. 14B. In FIG. 14B, the abscissa axis represents a period of time during which stress is applied, the ordinate axis represents surge current (A), Tr represents rise time (ns), and Td represents damping time (ns).
In the known semiconductor integrated circuit device shown in FIG. 13, during a normal operation, power supply voltage VDD and ground voltage VSS are applied to the power supply line 119 and the ground line 120, respectively. In carrying out an ESD test according to the HBM test standards, there are the case where positive and negative surges are applied to the external connection terminal 101 with the ground voltage VSS used as the reference and the case where positive and negative surges are applied to the external connection terminal 101 with the power supply voltage VDD used as the reference. The status in which the ground voltage VSS is used as the reference means that the voltage of the power supply line 119 is not fixed but placed in an open state and the voltage of the ground line 120 is fixed at the ground voltage VSS. On the other hand, the status in which the power supply voltage VDD is used as the reference means that the voltage of the power supply line 119 is fixed at the power supply voltage VDD and the voltage of the ground line 120 is not fixed but placed in an open state.
To describe the sub-circuit at the right-hand part of the evaluation circuit shown in FIG. 14A, the voltage between the two electrodes of the charge and discharge capacitor 151 is applied to the discharge resistor 153 and the semiconductor integrated circuit device (i.e., the device to be tested 154). At this time, the voltage dropped by the discharge resistor 153 is applied to the external connection terminal 101 connected to the output circuit 103, and an external connection circuit (not shown) connected to an input circuit.
However, if the known semiconductor integrated circuit device shown in FIG. 13 undergoes an ESD test that is carried out according to the HBM test standards (using the ground voltage VSS as the reference), the capabilities of the NMIS transistor 106 in the electrostatic discharge protection circuit 102 and the NMIS transistor 112 in the output circuit 103 to withstand high voltage might be degraded, and/or the NMIS transistors 106 and 112 might be destroyed.
Furthermore, in order to cut down the costs of an LSI chip, the NMIS transistors 106 and 112 have to be reduced in size. Hence, the capabilities of these transistors to withstand high voltage are more likely to be degraded, and/or these transistors are more likely to be destroyed.